Apparently, the Cupertino tech giant is getting ready to implement the technology on its upcoming products, which many assume to be the highly-anticipated iPhone 5 and iPad 3.
Macroscalar provide better support for the performance of a processor, while consuming less power.
Last year in July, ZDNet wrote an article in which they detailed Apple’s macroscalar architecture, explaining how the technology could help to improve the processor efficiency.
“The macroscalar processor addresses this problem in a new way: at compile-time it generates contingent secondary instructions so when a data-dependent loop completes the next set of instructions are ready to execute. In effect, it loads another pipeline for, say, completing a loop, so the pipeline remains full whether the loop continues or completes. It can also load a set of sequential instructions that run within or between loops, speeding execution as well.”
The patent summary describes an example of where “a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel.”
Here are some examples of software that Apple believes this processor might be featured on in the future:
“Computer software for personal information management; database management software; database synchronization software; character recognition software; voice recognition software; speech to text conversion software; voice-enabled software applications.”
Apple is likely to develop this type of architecture since the company designs its own processors, software and hardware.